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xr
APRIL 2005
PRELIMINARY
XRT91L82
REV. P1.0.5
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION
The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control FIGURE 1. BLOCK DIAGRAM OF XRT91L82
of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS
* SONET/SDH-based Transmission Systems * Add/Drop Multiplexers * Cross Connect Equipment * ATM and Multi-Service Switches, Routers and
Switch/Routers
* DSLAMS * SONET/SDH Test Equipment * DWDM Termination Equipment
STS-48 TRANSCEIVER OVERFLOW FIFO_RST WP 16x9 FIFO TXOP/N PISO (Parallel Input Serial Output) Re-Timer TXSCLKOP/N
TXDI[15:0]P/N
16
TXPCLKIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16SEL RLOOPP
RP Div by 16
CMU DLOOP RLOOPS
RXDO[15:0]P/N
SIPO (Serial Input Parallel Output)
CDR
RXIP/N
16
RXPCLKOP/N DISRD DISRDCLK Div by 16
TDO TDI TCK TMS TRST
JTAG
Serial Microprocessor
Hardware Control
PFD & Charge Pump
RLOOPS_PRBSCLR DLOOP LPTIME_NOJA
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
INTERM/VCXO_IN
RXCAP1P RXCAP1N/CPOUT
SE_REF SEREF_DIS
PRBS_EN PRBS_ERR
SDEXT POLARITY
TXSWING TXSCLKOOFF
LOCKDET_CMU
PIO_CFG [1:0]
LOCKDET_CDR
REF1CLKP/N REF2CLKP/N REFREQSEL1 REFREQSEL0
CDRLCKREF
CS SCLK SDI SDO HOST/HW
XRES1P
XRES1N
INT RESET
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.0.5
FEATURES
* 2.488 / 2.666 Gbps Transceiver * Targeted for SONET OC-48/SDH STM-16 Applications * Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of
2.666 Gbps
* Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, and clock data recovery (CDR) functions
* 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL signaling data paths running at 155.52/166.63
Mbps using internal input termination for reduced passive components on board
* Non-FEC and FEC rate REF1CLKP/N and REF2CLKP/N dual reference input ports * Supports 155.52/166.63MHz or 77.76/83.31MHz transmit and receive external reference input ports * Optional VCXO input port support multiple de-jittering modes in Host mode * On-chip phase detector and charge pump for external VCXO based de-jittering PLL * Internal FIFO decouples transmit parallel clock input and transmit parallel clock output * Provides Local, Remote Serial and Remote Parallel Loopback modes as well as Loop Timing mode * Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect * Host mode serial microprocessor interface simplifies monitor and control * Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance
specification, GR-253 CORE, GR-253-ILR- SONET Jitter specifications.
* Operates at 1.8V CMOS and CML Power with 3.3V I/O * 500mW Typical Power Dissipation using LVDS Interface * Package: 15 x 15 mm 196-pin STBGA * IEEE 1149.1 Compatable JTAG port PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRT91L82IB PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40 to +85 C C
2
REV. P1.0.5
xr xr xr xr
FIGURE 2. 196 BGA PINOUT OF THE XRT91L82 (TOP VIEW)
A
GND
RXIP
RXIN
VDD_CML
TXON
TXOP
VDD_CML TXSCLKON TXSCLKOP
VDD_CML
REF2CLKP
VDD_CML
REF1CLKP
GND
B
GND
GND
VDD_CML
GND
VDD_CML
GND
VDD_CML
GND
VDD_CML
GND
REF2CLKN
GND
REF1CLKN
GND
TXSCLKOOFF LOOPTM_NOJA C AVDD_RX SDEXT SEREFDIS TXCLKO16SEL LOCKDET_CDR LOCKDET_CMU DISRD D GND AVDD_RX PIO_CFG1 /PRBS_LOCK INTERM E RXCAP1P RXCAP1N F / CP_OUT G GND AVDD_RX VDD_IO RXDO0N RXDO0P GND TXDI15N TXDI15P VDD_IO TXDI13N GND VDD_CMOS GND VDD_CMOS GND VDD_CMOS GND VDD_CMOS GND GND PIO_CFG0 / VCXO_IN RESET VDD_CMOS GND VDD_CMOS / SDO PRBS_ERR POLARITY (I2C - SCL) TXDI14P GND XRES1N FIFO_RST OVERFLOW TDO TMS PRBS_EN / INT (I2C - SDA) DLOOP REFREQSEL0 GND XRES1P / SCLK TCK TDI / CS / SDI TXSWING DISRDCLK REFREQSEL1 AVDD_TX GND VDD_CML CDRLCKREF VDD_CML AVDD_TX
RLOOPS_PRBSCLR
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TXDI13P
TXDI14N
AVDD_TX
GND
H AVDD_RX
GND
RXDO1N
RXDO1P
GND
RXDO2N
RXDO2P
RXDO3P
TXDI11P
GND
TXDI12N
TXDI12P
GND
AVDD_TX
3
J
VDD_IO
RXDO4N
RXDO4P
VDD_CMOS
RXDO5N
RXDO5P
VDD_CMOS RXDO3N
TXDI11N
TXDI9P
VDD_IO
TXDI10N
TXDI10P
TXDI8P
K RXDO6N
RXDO6P
VDD_IO
RXDO7N
RXDO7P
VDD_IO
RXDO8N
RXDO8P
VDD_IO
TXDI9N
TXDI7N
TXDI7P
VDD_IO
TXDI8N
L
GND
RXDO9N
RXDO9P
GND
RXDO10N
RXDO10P
SE_REF
RXDO11P
TXDI5N
TXDI5P
GND
TXDI6N
TXDI6P
GND
M RXDO12N
RXDO12P
VDD_IO
RXDO13N
RXDO13P
VDD_CMOS
RXDO14P
RXDO11N
VDD_CMOS
TXDI3N
TXDI3P
VDD_CMOS
TXDI4N
TXDI4P
N
VDD_IO
HOST/HW
TRST
VDD_IO
RXDO15N
RXDO15P
RXDO14N
GND
TXDI1N
TXDI1P
VDD_IO
TXDI2N
TXDI2P
VDD_IO
P TXCLKO16NTXCLKO16P
GND
RXPCLKON
RXPCLKOP
GND
TXPCLKON TXPCLKOP
GND
TXPCLKIN
TXPCLKIP
GND
TXDI0N
TXDI0P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XRT91L82
REV. P1.0.5
PRELIMINARY TABLE OF CONTENTS
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L82 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2
PRODUCT ORDERING INFORMATION ..................................................................................................2
FIGURE 2. 196 BGA PINOUT OF THE XRT91L82 (TOP VIEW).......................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS ..........................................................................................................4
COMMON CONTROL .....................................................................................................................................4 TRANSMITTER SECTION ..................................................................................................................................8
RECEIVER SECTION.......................................................................................................................................11
SERIAL MICROPROCESSOR INTERFACE .............................................................................................14 ...................................................................................................................................................................14 JTAG ..........................................................................................................................................................15 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................16
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 16 1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 16
TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE)...................................................................................... 16
1.3 ALTERNATE CLOCK INPUT REFERENCE (HOST MODE ONLY) .............................................................. 16
TABLE 2: ALTERNATE REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE) ................................................................... 17
1.4 DATA LATENCY ............................................................................................................................................. 17
TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 17
1.5 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 17
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 17
1.6 PRBS PATTERN GENERATOR AND ANALYZER ....................................................................................... 17
2.0 RECEIVE SECTION .............................................................................................................................18
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 18
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 18 TABLE 4: DIFFERENTIAL CML INPUT SWING PARAMETERS .............................................................................................................. 18
2.2 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19
FIGURE 5. EXTERNAL LOOP FILTER ................................................................................................................................................ 19
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 19
TABLE 5: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 20
2.4 EXTERNAL SIGNAL DETECTION ................................................................................................................. 20
TABLE 6: LOSD DECLARATION POLARITY SETTING ......................................................................................................................... 20
2.5 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 21
FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 21
2.6 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21
FIGURE 7. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 21
2.7 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 22
FIGURE 8. LVDS EXTERNAL BIASING RESISTORS............................................................................................................................. 22
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD ........................................................ 22 2.9 PARALLEL RECEIVE CLOCK OUTPUT DISABLE ...................................................................................... 22 2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22
FIGURE 9. RECEIVE PARALLEL OUTPUT TIMING .............................................................................................................................. 22 TABLE 7: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS ........................................................................... 22
3.0 TRANSMIT SECTION ..........................................................................................................................23
3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 23
FIGURE 10. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 23
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 24
FIGURE 11. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 24 TABLE 8: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION............................................................................... 24 TABLE 9: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION ........................................................................................... 24
3.3 TRANSMIT FIFO ............................................................................................................................................. 24
FIGURE 12. TRANSMIT FIFO AND SYSTEM INTERFACE .................................................................................................................... 25
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 25 3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 25
I
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PRELIMINARY
XRT91L82
REV. P1.0.5
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
TABLE 10: CLOCK MULTIPLIER UNIT PERFORMANCE ....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 26
TABLE 11: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS ............................................................................................ 27 FIGURE 14. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO (HOST MODE ONLY) .......................................................... 27
3.8 EXTERNAL LOOP FILTER (HOST MODE ONLY) ........................................................................................ 28
FIGURE 15. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER .................................................................................................. 28
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
FIGURE 16. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 28 TABLE 12: DIFFERENTIAL CML OUTPUT SWING PARAMETERS......................................................................................................... 28 FIGURE 17. CML DIFFERENTIAL VOLTAGE SWING........................................................................................................................... 29
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 30
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 30
FIGURE 18. SERIAL REMOTE LOOPBACK......................................................................................................................................... 30
4.2 PARALLEL REMOTE LOOPBACK (HOST MODE ONLY) ........................................................................... 30
FIGURE 19. PARALLEL REMOTE LOOPBACK .................................................................................................................................... 30
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
FIGURE 20. DIGITAL LOOPBACK...................................................................................................................................................... 31
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 32
4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 32 FIGURE 21. JITTER TOLERANCE MASK............................................................................................................................................ 32 FIGURE 22. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 ............................ 33 FIGURE 23. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ..................................... 33 4.4.2 JITTER TRANSFER .................................................................................................................................................... 33 FIGURE 24. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16 .............................. 33 FIGURE 25. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE ....................................... 33 4.4.3 JITTER GENERATION................................................................................................................................................ 34 FIGURE 26. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS .............................. 34 FIGURE 27. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.666 GBPS .............................. 34
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 35
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 35
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 35
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 35
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 36
5.2.1 5.2.2 5.2.3 5.2.4 R/W (SCLK1)............................................................................................................................................................... A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. X (DUMMY BIT SCLK8) .............................................................................................................................................. D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 36 36 36 36
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 36
6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 37
TABLE 13: TABLE 14: TABLE 15: TABLE 16: TABLE 17: TABLE 18: TABLE 19: TABLE 20: TABLE 21: TABLE 22: TABLE 23: TABLE 24: MICROPROCESSOR REGISTER MAP................................................................................................................................ 37 MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 38 MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 39 MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 40 MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 41 MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 42 MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ................................................................................................. 43 MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION ................................................................................................. 45 MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION ................................................................................................. 46 MICROPROCESSOR REGISTER 0X3CH BIT DESCRIPTION................................................................................................. 48 MICROPROCESSOR REGISTER 0X3DH BIT DESCRIPTION................................................................................................. 49 MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION ................................................................................................. 49
7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 50 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 50 ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS ............................................................. 50 POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 50 LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 51 LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 51 LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ........................................................... 52 ORDERING INFORMATION .................................................................................................................. 53 196 SHRINK THIN BALL GRID ARRAY .............................................................................................. 53 (15.0 MM X 15.0 MM, STBGA).......................................................................................................... 53
II
XRT91L82
REV. P1.0.5
PRELIMINARY
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.00.......................................................................................................................................... 53 REVISION HISTORY.......................................................................................................................................54
III
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REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PIN DESCRIPTIONS
COMMON CONTROL
NAME RESET LEVEL LVTTL, LVCMOS TYPE I PIN E5 DESCRIPTION Master Reset Input Active low signal. When this pin is pulled "Low" for more than 30ns, the internal registers are set to their default state. See the register description for the default values. This pin is provided with an internal pull-up. Parallel I/O Configuration Selects parallel I/O to be differential LVDS, differential LVPECL, or Single-Ended LVPECL based on table below.
PIO_CFG [1:0] 00 VDD_I/O Input Configuration 3.3V Differential LVPECL 3.3V Single-Ended LVPECL 3.3V Differential LVDS Reserved Output Configuration 3.3V Differential LVPECL 3.3V Single-Ended LVPECL 3.3V Differential LVDS
PIO_CFG1 PIO_CFG0
LVTTL, LVCMOS
I
D3 E3
3.3V
01
3.3V
10
3.3V
11
This pin is provided with an internal pull-down. XRES1P XRES1N I E14 F14 External LVDS Biasing Resistors A 402 resistor with +/-1% tolerance should be placed across these 2 pins for proper biasing. Although unecessary in LVPECL operation, this resistor is required in LVDS operation. See Figure 8 on page 22. Single-Ended LVPECL Biasing Output Reference VBB 100K output bias reference. Maximum load capacitance is 30pF. Maximum sourcing/sinking capability is 750A and 1000A respectively. SE_REF Power down Control Powers down SE_REF and reduces power consumption. "Low" = SE_REF Enabled "High" = SE_REF Disabled This pin is provided with an internal pull-up. Reference Clock Input 1 This differential clock input reference is used for the transmit clock multiplier unit (CMU) and clock data recovery (CDR) to provide the necessary high-speed clock reference for this device. Pin REFREQSEL[1:0] determines the value used as the reference. See Pin REFREQSEL[1:0] for more details. Internally terminated and biased.
SE_REF
Analog
O
L7
SEREFDIS
LVTTL, LVCMOS
I
C3
REF1CLKP REF1CLKN
LVPECL Diff
I
A13 B13
4
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER COMMON CONTROL
NAME REF2CLKP REF2CLKN LEVEL LVPECL Diff TYPE I PIN A11 B11 DESCRIPTION
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REV. P1.0.5
Reference Clock Input 2 This differential clock input reference is used for the transmit clock multiplier unit (CMU) and clock data recovery (CDR) to provide the necessary high-speed clock reference for this device. Pin REFREQSEL[1:0] determines the value used as the reference. See Pin REFREQSEL[1:0] for more details. Internally terminated and biased. Reference Clock Frequency Select Hardware Mode REFREQSEL1 pin is used to select the frequency of the REF1CLK and/or REF2CLK input to the CMU and CDR.
REFREQSEL [1:0] 00 CMU
REFERENCE FREQUENCY
REFREQSEL1 / SCLK
LVTTL, LVCMOS
I
D12
CDR
REFERENCE FREQUENCY
155.52 MHz present on 155.52 MHz present on REF1CLK REF1CLK REF2CLK not used REF2CLK not used 155.52 MHz present on 166.63 MHz present on REF1CLK REF2CLK 166.63 MHz present on 155.52 MHz present on REF2CLK REF1CLK 166.63 MHz present on 166.63 MHz present on REF2CLK REF2CLK REF1CLK not used REF1CLK not used
01 10 11
NOTE: Non-FEC rates require 155.52 MHz clock reference. FEC rates require 166.63 MHz clock reference This pin is provided with an internal pull-down.
Host Mode This pin is functions as the microprocessor Serial Clock Input. REFREQSEL0 LVTTL, LVCMOS I E12 Reference Clock Frequency Select REFREQSEL0 pin is used to select the frequency of the REF1CLK and/or REF2CLK input to the CMU and CDR.
REFREQSEL [1:0] 00 CMU
REFERENCE FREQUENCY
CDR
REFERENCE FREQUENCY
155.52 MHz present on 155.52 MHz present on REF1CLK REF1CLK REF2CLK not used REF2CLK not used 155.52 MHz present on 166.63 MHz present on REF1CLK REF2CLK 166.63 MHz present on 155.52 MHz present on REF2CLK REF1CLK 166.63 MHz present on 166.63 MHz present on REF2CLK REF2CLK REF1CLK not used REF1CLK not used
01 10 11
NOTE: Non-FEC rates require 155.52 MHz clock reference. FEC rates require 166.63 MHz clock reference This pin is provided with an internal pull-down.
5
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
LEVEL LVTTL, LVCMOS TYPE I PIN D9 DESCRIPTION 223-1 PRBS TEST Pattern Enable Generates 223-1 Pseudo Random Binary Sequence test patterns and analyzes in the receiving block for proper reception. "Low" = Normal Mode "High" = PRBS pattern generator and analyzer Enabled. NOTE: A Local Loopback of some type such as Digital Local Loopback or an optical cable loopback is expected to be used in conjunction with PRBS_EN in order for the PRBS analyzer to receive the PRBS pattern. This pin is provided with an internal pull-down.
COMMON CONTROL
NAME PRBS_EN
PRBS_ERR /SDO
LVCMOS
O
E9
223-1 PRBS Pattern Validation Error Hardware Mode Indicates an error condition has occurred/is occuring in the validation of generated PRBS pattern. "Low" = Un-erred transmission and reception of PRBS pattern. "High" = Error Condition occurrence. Host Mode This pin is functions as the microprocessor Serial Data Output.
RLOOPS_ PRBSCLR
LVTTL, LVCMOS
I
F11
Serial Remote Loopback Normal Mode The serial remote loopback mode interconnects the receive serial data input to the transmit serial data output. If serial remote loopback is enabled, the 16-bit parallel transmit data input is ignored while the 16-bit parallel receive data output and parallel receive clock output is maintained. "Low" = Serial Remote Loopback Mode Enabled "High" = Disabled PRBSTest Mode When PRBS_EN is asserted, this bit is used to clear or reset PRBS_ERR error condition. Serial Remote Loopback is not available in PRBS Test Mode. "Low" = Clears PRBS_ERR condition "High" = Normal Mode This pin is provided with an internal pull-up.
6
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER COMMON CONTROL
NAME DLOOP LEVEL LVTTL, LVCMOS TYPE I PIN E11 DESCRIPTION
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REV. P1.0.5
Digital Local Loopback The digital local loopback mode interconnects the 16-bit parallel transmit data and parallel transmit clock input to the 16-bit parallel receive data and parallel receive clock output respectively while maintaining the transmit serial data output. If digital local loopback is enabled, the receive serial data input is ignored. "Low" = Digital Local Loopback Mode Enabled "High" = Disabled This pin is provided with an internal pull-up.
LOOPTM_NOJA / SDI
LVTTL, LVCMOS
I
C10
Loop Timing Mode With No Jitter Attenuation Hardware Mode When the loop timing mode is activated, the external local reference clock input to the CMU is replaced with the 1/16th of the high-speed recovered receive clock coming from the CDR. "Low" = Disabled "High" = Loop timing Activated This pin is provided with an internal pull-down. Host Mode This pin is functions as the microprocessor Serial Data Input.
7
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
LEVEL LVDS, LVPECL Diff and SE TYPE I PIN P14 P13 N10 N9 N13 N12 M11 M10 M14 M13 L10 L9 L13 L12 K12 K11 J14 K14 J10 K10 J13 J12 H9 J9 H12 H11 G11 G10 F12 G12 G8 G7 A6 A5 DESCRIPTION Transmit Parallel Data Input The 155.52 Mbps 16-bit parallel transmit data input should be applied to the transmit parallel bus simultaneously to be sampled at the rising edge of the TXPCLKIP/N input. The 16-bit parallel interface is multiplexed into the transmit serial output interface, MSB first (TXDI15P/N). TXDI[15:0]P/N 100 internal termination is controlled by INTERM pin or register bit. Inputs are internally biased to VDD_IO - 1V for AC coupled applications. For LVPECL Single-Ended applications, either a 100K VBB bias reference must be provided or the SE_REF pin can also be used to bias and connected all the negative polarity "N" pins. NOTE: The XRT91L82 can accept 166.63 Mbps 16-bit parallel transmit data input for Forward Error Correction (FEC) Applications.
TRANSMITTER SECTION
NAME TXDI0P TXDI0N TXDI1P TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N TXDI4P TXDI4N TXDI5P TXDI5N TXDI6P TXDI6N TXDI7P TXDI7N TXDI8P TXDI8N TXDI9P TXDI9N TXDI10P TXDI10N TXDI11P TXDI11N TXDI12P TXDI12N TXDI13P TXDI13N TXDI14P TXDI14N TXDI15P TXDI15N TXOP TXON
CMLDIFF
O
Transmit Serial Data Output The transmit serial data output stream is generated by multiplexing the 16-bit parallel transmit data input into a 2.488 Gbps serial data output stream. In Forward Error Correction, the transmit serial data output stream is 2.666 Gbps. Transmit Serial CML Output Swing Mode Hardware Mode Selects the generated transmit serial CML Output swing to the optical module. "Low" = Low Swing CML Mode "High" = High Swing CML Mode This pin is provided with an internal pull-up. Host Mode This pin is functions as the microprocessor Interrupt Output. NOTE: This pin becomes an open drain output in Host Mode and requires an external pull-up resistor.
TXSWING / INT
LVTTL, LVCMOS
I/O
D10
8
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TRANSMITTER SECTION
NAME TXSCLKOP TXSCLKON TXSCLKOOFF / CS LEVEL CMLDIFF TYPE O PIN A9 A8 C9 DESCRIPTION
xr
REV. P1.0.5
2.488/2.666 GHz Transmit Serial Clock Output A high-speed 2.488/2.666 GHz Transmit serial clock output that can be used to retime TXOP/N. 2.488/2.666 GHz Hi-speed Serial Clock Output Tristate Hardware Mode Tristates TXSCLKOP/N output and reduces power consumption. "Low" = TXSCLKOP/N output Enabled "High" = Tristates TXSCLKOP/N output This pin is provided with an internal pull-up. Host Mode This pin is functions as the microprocessor Chip Select Input.
LVTTL, LVCMOS
I
INTERM / VCXO_IN
LVTTL, LVCMOS / SELVCMOS
I
E4
Transmit Parallel Bus Input Internal Termination Hardware Mode Provides 100 line-to-line internal termination to TXDI[15:0]P/N and TXPCLKIP/N. "Low" = Disabled "High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated. This pin is provided with an internal pull-down. Host Mode - Voltage Controled 77.76/83.31 MHz or 155.52/ 166.63 MHz External Oscillator Input This 77.76/83.31 MHz or 155.52/166.63 MHz Single-Ended LVCMOS clock input is used for the transmit PLL jitter attenuation. ALTFREQSEL register bit determines the value used as the reference. Software register bit VCXOSEL allows the selection of the De-Jitter VCXO Mode. See ALTFREQSEL and VCXO_SEL software register bit description for more details.
TXPCLKIP TXPCLKIN
LVDS, LVPECL Diff and SE
I
P11 P10
Transmit Parallel Clock Input 155.52 MHz clock input used to sample the 16-bit parallel transmit data input TXDI[15:0]P/N. TXPCLKIP/N 100 internal termination is controlled by INTERM pin or register bit. TXPCLKIP/N inputs are internally biased to VDD_IO - 1V for AC coupled application. NOTE: The XRT91L82 can accept a 166.63 MHz transmit clock input for Forward Error Correction (FEC) Applications.
TXPCLKOP TXPCLKON
LVDS, LVPECL Diff and SE
O
P8 P7
Transmit Parallel Clock Output This 155.52 MHz clock can be used for the downstream device to generate the TXDI[15:0]P/N data and TXPCLKIP/N clock input. This enables the downstream device and the STS-48 transceiver to be in synchronization. NOTE: The XRT91L82 can output a 166.63 MHz transmit clock output for Forward Error Correction (FEC).
9
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
LEVEL LVDS, LVPECL Diff and SE TYPE O PIN P2 P1 DESCRIPTION Auxiliary Clock Output (155.52/19.44 MHz) 155.52 or 19.44 MHz auxiliary clock derived from CMU output. This clock can also be used for the downstream device as a reference for generating the TXDI[15:0]P/N data and TXPCLKIP/ N clock input. This enables the downstream device and the STS-48 transceiver to be in synchronization. The frequency output of this pin is controlled by TXCLKO16SEL. NOTE: This pin can output a 166.63/20.83 MHz transmit clock output for Forward Error Correction (FEC).
TRANSMITTER SECTION
NAME TXCLKO16P TXCLKO16N
TXCLKO16SEL
LVTTL, LVCMOS
I
C4
Auxiliary Clock Output Select This pin is used to select the auxiliary clock output. "Low" = TXCLKO16P/N outputs 155.52/ 166.63 MHz "High" = TXCLKO16P/N outputs 19.44/ 20.83 MHz This pin is provided with an internal pull-down. CMU Lock Detect This pin is used to monitor the lock condition of the clock multiplier unit. "Low" = CMU Out of Lock "High" = CMU Locked Transmit FIFO Overflow This pin is used to monitor the transmit FIFO status. "Low" = Normal Status "High" = Overflow Condition FIFO Control Reset FIFO_RST should be held "High" for a minimum of 2 TXPCLKOP/N cycles after powering up and during manual FIFO reset. After the FIFO_RST pin is returned "Low," it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an interrupt indication that the FIFO has an overflow condition, this pin is used to reset or flush out the FIFO. "Low" = Normal Operation "High" = Manual FIFO Reset This pin is provided with an internal pull-down. NOTES:
LOCKDET_CMU
LVCMOS
O
C6
OVERFLOW
LVCMOS
O
D6
FIFO_RST
LVTTL, LVCMOS
I
D5
1. In Hardware Mode, to automatically reset the FIFO, tie the
OVERFLOW output pin to the FIFO_RST input pin or if desired, an asynchronous FIFO reset pin and the OVERFLOW output pin can be logically 'OR'ed and the output tied to the FIFO_RST input pin. 2. In Host Mode, this pin is disabled and not used. FIFO_RST is asserted through Microprocessor Control Register 0x03H Bit-D0. A FIFO_AUTORST bit is also available on Microprocessor Control Register 0x03H BitD1.
10
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION
NAME RXDO0P RXDO0N RXDO1P RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N RXDO4P RXDO4N RXDO5P RXDO5N RXDO6P RXDO6N RXDO7P RXDO7N RXDO8P RXDO8N RXDO9P RXDO9N RXDO10P RXDO10N RXDO11P RXDO11N RXDO12P RXDO12N RXDO13P RXDO13N RXDO14P RXDO14N RXDO15P RXDO15N RXIP RXIN LEVEL LVDS, LVPECL Diff and SE TYPE O PIN G5 G4 H4 H3 H7 H6 H8 J8 J3 J2 J6 J5 K2 K1 K5 K4 K8 K7 L3 L2 L6 L5 L8 M8 M2 M1 M5 M4 M7 N7 N6 N5 A2 A3 DESCRIPTION
xr
REV. P1.0.5
Receive Parallel Data Output 155.52 Mbps 16-bit parallel receive data output is updated simultaneously on the falling edge of the RXPCLKOP/N output. The 16-bit parallel interface is de-multiplexed from the receive serial data input, MSB first (RXDO15P/N). For LVPECL SingleEnded applications, all the negative polarity "N" pins should not be connected. NOTE: The XRT91L82 can output 166.63 Mbps 16-bit parallel receive data output for Forward Error Correction (FEC) Applications.
CMLDIFF
I
Receive Serial Data Input The receive serial data stream of 2.488 Gbps is applied to these input pins. In Forward Error Correction, the receive serial data stream is 2.666 Gbps. This pin is internally biased and terminated. Receive Parallel Clock Output 155.52 MHz parallel clock output used to update the 16-bit parallel receive data output RXDO[15:0]P/N at the falling edge of this clock. NOTE: The XRT91L82 can output a 166.63 MHz receive clock output for Forward Error Correction (FEC).
RXPCLKOP RXPCLKON
LVDS, LVPECL Diff and SE
O
P5 P4
11
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
LEVEL LVTTL, LVCMOS TYPE I PIN C12 DESCRIPTION CDR's Recovered High-speed Serial Clock Reference Controls CDR's operation. "Low" = Forced to lock to CDR PLL reference training clock "High" = Normal Operation (Locked to incoming serial data) This pin is provided with an internal pull-up. Receive Parallel Data Output Disable Hardware Mode If this pin is set to "0", the 16-bit parallel receive data output will asynchronously mute. "Low" = Forces RXDO[15:0]P/N to a logic state of "0" "High" = Normal Mode This pin is provided with an internal pull-up. Host Mode 223-1 PRBS Pattern Lock Output Indicator This pin indicates the current state condition of the PRBS pattern analyzer when the PRBS pattern generator is enabled. "Low" = PRBS pattern analyzer currently Out of Lock "High" = PRBS pattern analyzer currently Locked
RECEIVER SECTION
NAME CDRLCKREF
DISRD /PRBS_LOCK
LVTTL, LVCMOS
I/O
D4
DISRDCLK
LVTTL, LVCMOS
I
D11
Receive Parallel Clock Output Disable This pin is used to asynchronously control the activity of the parallel receive clock output. "Low" = Forces RXPCLKOP/N to a logic state of "0" "High" = Normal Mode This pin is provided with an internal pull-up. CDR Lock Detect This pin is used to monitor the lock condition of the clock and data recovery unit. "Low" = CDR Out of Lock "High" = CDR Locked Signal Detect Input from Optical Module When inactive, it will automatically mute received data output bus RXDO[15:0]P/N upon Loss of Signal Detection (LOSD) condition. "Active" = Normal Operation (SDEXT detects signal presence) "Inactive" =Mutes upon LOSD (SDEXT detects signal absence) This pin is provided with an internal pull-up. Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "Low" = SDEXT is active "Low" "High" = SDEXT is active "High" This pin is provided with an internal pull-up.
LOCKDET_CDR
LVCMOS
O
C5
SDEXT
LVTTL, LVCMOS
I
C2
POLARITY
LVTTL, LVCMOS
I
E10
12
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER RECEIVER SECTION
NAME RXCAP1P LEVEL Analog TYPE I PIN E1 DESCRIPTION
xr
REV. P1.0.5
External Receive Loop Filter Hardware Mode This pin is required for the external loop filter capacitor and resistors. See Figure 5 on page 19. Host Mode - No Connect This pin is not connected in Host Mode.
RXCAP1N / CP_OUT
Analog
I/O
F1
External Receive Loop Filter Hardware Mode This pin is required for the external loop filter capacitor and resistors. See Figure 5 on page 19. Host Mode - Charge Pump Output (for external VCXO) The nominal output of the charge pump current is 250A.
POWER AND GROUND
NAME AVDD_RX TYPE PWR PIN C1, D2, G2, H1 DESCRIPTION Analog 1.8V Receiver Power Supply AVDD_RX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD_RX power supply pins should have bypass capacitors to the nearest ground. Analog 1.8V Transmitter Power Supply AVDD_TX should be isolated from the digital power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD_TX power supply pins should have bypass capacitors to the nearest ground. CML 1.8V Power Supply These pins require a 1.8V potential. Digital 1.8V Power Supply VDD_CMOS should be isolated from the analog power supplies. For best results, use a ferrite bead along with an internal power plane separation. The VDD_CMOS power supply pins should have bypass capacitors to the nearest ground. 3.3V LVPECL/ 3.3V LVDS Input /Output Bus Power Supply and 3.3V Digital I/O Power Supply These pins require a 3.3V potential in LVPECL or LVDS operation. These pins also power the 3.3V Digital I/O Power Supply. Ground for 3.3V / 1.8V Digital Power Supplies It is recommended that all ground pins of this device be tied together.
AVDD_TX
PWR
C14, D13, G13, H14
VDD_CML
PWR
A4, A7, A10, A12, B3, B5, B7, B9, C11, C13 E6, E8, F3, F5, F7, F9, J4, J7, M6, M9, M12
VDD_CMOS
PWR
VDD_IO
PWR
G3, G9, J1, J11, K3, K6, K9, K13, M3, N1, N4, N11, N14
GND
GND
A1, A14, B1, B2, B4, B6, B8, B10, B12, B14, D1, D14, E2, E7, E13, F2, F4, F6, F8, F10, F13, G1, G6, G14, H2, H5, H10, H13, L1, L4, L11, L14, N8, P3, P6, P9, P12
NOTE: For VDDIO=3.3V, all input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only.
13
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
SERIAL MICROPROCESSOR INTERFACE
NAME HOST/HW LEVEL LVTTL, LVCMOS TYPE I PIN N2 DESCRIPTION Host or Hardware Mode Select Input The XRT91L82 offers two modes of operation for interfacing to the device. The Host mode uses a serial microprocessor interface for programming individual registers. The Hardware mode is controlled by the state of the hardware pins set by the user. When left unconnected, by default, the device is configured in the Hardware mode. "Low" = Hardware Mode "High" = Host Mode This pin is provided with an internal pull-down. Chip Select Input (Host Mode Only) Active "Low" signal. This signal enables the serial microprocessor interface by pulling chip select "Low". The serial microprocessor is disabled when the chip select signal returns "High". NOTES:
TXSCLKOOFF / CS
LVTTL, LVCMOS
I
C9
1. The serial microprocessor interface does not support burst
mode. Chip Select must be de-asserted after each operation cycle. 2. Chip Select is only active in Host Mode. This pin is provided with an internal pull-up. REFREQSEL1 / SCLK LVTTL, LVCMOS I D12 Serial Clock Input (Host Mode Only) Once CS is pulled "Low", the serial microprocessor interface requires 16 clock cycles for a complete Read or Write operation. Serial Clock Input is only active in Host Mode. This pin is provided with an internal pull-down. Serial Data Input (Host Mode Only) When CS is pulled "Low", the serial data input is sampled on the rising edge of SCLK. Serial Data Input is only active in Host Mode. This pin is provided with an internal pull-down. Serial Data Output (Host Mode Only) If a Read function is initiated, the serial data output is updated on the falling edge of SCLK8 through SCLK15, with the LSB (D0) updated first. This enables the data to be sampled on the rising edge of SCLK9 through SCLK16. Serial Data Output is only active in Host Mode. Interrupt Output (Host Mode Only) Active "Low" signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". Interrupt Output is only active in Host Mode. NOTE: This pin is an open drain output and requires an external pull-up resistor.
LOOPTM_NOJA / SDI
LVTTL, LVCMOS
I
C10
PRBS_ERR / SDO
LVCMOS
O
E9
TXSWING / INT
LVCMOS
O
D10
14
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JTAG
SIGNAL NAME TCK TMS PIN # C7 D8 TYPE I I DESCRIPTION Test clock: Boundary Scan Clock Input. This pin is provided with an internal pull-down.
xr
REV. P1.0.5
Test Mode Select: Boundary Scan Mode Select Input. JTAG is disabled by default. Note: This input pin should be pulled "Low" for JTAG operation This pin is provided with an internal pull-up. Test Data In: Boundary Scan Test Data Input This pin is provided with an internal pull-up. Test Data Out: Boundary Scan Test Data Output JTAG Test Reset Input Note: This input pin should be pulled "Low" to reset JTAG This pin is provided with an internal pull-up.
TDI TDO TRST
C8 D7 N3
I O I
NO CONNECTS
NAME None LEVEL N/A TYPE N/A PIN None DESCRIPTION No Connect This pin can be left floating or tied to ground.
15
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
1.0 FUNCTIONAL DESCRIPTION The XRT91L82 Transceiver is designed to operate with a SONET Framer/ASIC device and provide a highspeed serial interface to optical networks. The Transceiver converts 16-bit parallel data at 155.52/166.63 MHz to a serial CML bit stream at 2.488/2.666 Gbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-serialization (SerDes), and receive clock and data recovery (CDR) unit. The Transceiver is divided into Transmit and Receive sections and is used to provide the front end component of SONET equipment, which includes primarily serial transmit and receive functions. 1.1 Hardware Mode vs. Host Mode Functionality of the STS-48/STM-16 Transceiver can be configured by using either Host mode or Hardware mode. Hardware mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected. The transceiver functionality is then controlled by the hardware pins described in the Hardware Pin Descriptions. However, if Host mode is selected by pulling HOST/HW "High", the functionality is controlled by programming internal R/W registers using the Serial Microprocessor interface. Whether using Host or Hardware mode, the functionality remains the same. Therefore, the following sections describe the functionality rather than how each function is controlled. The Hardware Pin Descriptions and the Register Bit Descriptions concentrate on configuring the device. 1.2 Clock Input Reference The XRT91L82 can accept both 155.52 MHz non-FEC or 166.63 MHz FEC clock input at REF1CLKP/N and/or REF2CLKP/N as its internal timing reference for generating higher speed clocks. The reference clock can be provided with one of two frequencies chosen by REFREQSEL[1:0]. The reference frequency options for the XRT91L82 are listed in Table 1. TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE)
REFREQSEL CMU REFERENCE CDR REFERENCE CLOCK CLOCK [1:0] FREQUENCY FREQUENCY
00 REF1CLK REF1CLK
REF1CLK CLOCK FREQUENCY
155.52 MHz non-FEC 155.52 MHz non-FEC 155.52 MHz non-FEC not used
REF2CLK CLOCK FREQUENCY
not used
TRANSMIT DATA RATE
2.488 Gbps non-FEC 2.488 Gbps non-FEC 2.666 Gbps FEC 2.666 Gbps FEC
RECEIVE DATA RATE
2.488 Gbps non-FEC 2.666 Gbps FEC 2.488 Gbps non-FEC 2.666 Gbps FEC
01
REF1CLK
REF2CLK
166.63 MHz FEC 166.63 MHz FEC 166.63 MHz FEC
10
REF2CLK
REF1CLK
11
REF2CLK
REF2CLK
1.3
Alternate Clock Input Reference (Host Mode Only)
In Host mode, the XRT91L82 has the option to accept a lower reference frequency of 77.76 MHz non-FEC or 83.31 MHz FEC clock input at REF1CLKP/N and/or REF2CLKP/N. To use this feature, register bit ALTFREQSEL must be set "Low" on bit- D5 of "Configuration Control Register (0x07h)". The alternate reference frequency options are listed below in Table 2.
16
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.0.5
TABLE 2: ALTERNATE REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE)
REFREQSEL CMU REFERENCE CDR REFERENCE CLOCK CLOCK [1:0] FREQUENCY FREQUENCY
00 REF1CLK REF1CLK
REF1CLK CLOCK FREQUENCY
77.76 MHz non-FEC 77.76 MHz non-FEC 77.76 MHz non-FEC not used
REF2CLK CLOCK FREQUENCY
not used
TRANSMIT DATA RATE
2.488 Gbps non-FEC 2.488 Gbps non-FEC 2.666 Gbps FEC 2.666 Gbps FEC
RECEIVE DATA RATE
2.488 Gbps non-FEC 2.666 Gbps FEC 2.488 Gbps non-FEC 2.666 Gbps FEC
01
REF1CLK
REF2CLK
83.31 MHz FEC 83.31 MHz FEC 83.31 MHz FEC
10
REF2CLK
REF1CLK
11
REF2CLK
REF2CLK
1.4
Data Latency
Due to different operating modes and data logic paths through the device, there is an associated latency from data ingress to data egress. Table 3 specifies the data latency for a typical path. TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY
MODE OF OPERATION
Thru-mode
DATA PATH
Data on TXDI[15:0]P/N to data on TXOP/N
CLOCK REFERENCE
REF1CLKP/N or REF2CLKP/N Clock
MAXIMUM REFNCLK CLOCK CYCLES
18 to 20
1.5
Forward Error Correction (FEC)
Forward Error Correction is used to control errors along a one-way path of communication. FEC sends extra information along with data which can be used by a receiver to check and correct the data without requesting re-transmission of the original information. It does so by introducing a known structure into a data sequence prior to transmission. The most common methods are to replace a 14-bit data packet with a 15-bit codeword structure, or to replace a 17-bit data packet with an 18-bit codeword structure. The XRT91L82 supports FEC by accepting a clock input reference frequency of 83.31 or 166.63 MHz. Both reference frequencies allows the transmit 16-bit parallel data input to be applied to the STS-48 transceiver at 166.63 Mbps which is converted to a 2.666 Gbps serial output stream to an optical module. A simplified block diagram of FEC is shown in Figure 3. FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION
FEC codec
SONET/Framer ASIC
16
STS-48 Transceiver
Optical Module
Optical Module
STS-48 Transceiver
16
FEC codec
Optical Fiber
SONET/Framer ASIC
16
16
1.6
PRBS Pattern Generator and Analyzer
The XRT91L82 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. With the PRBS_EN asserted, the transmitter will send out PRBS pattern of 223-1 in STS48/48c or STM-16 rate. At the same time, the receiver PRBS detector is also enabled. Whenever the PRBS detector is not in sync, the PRBS_ERR bit will be set to "1". To clear the erred condition, PRBSCLR must be toggled "Low." If the correct PRBS pattern is detected by the receiver, then PRBS_ERR pin will go "Low" to indicate PRBS synchronization has been achieved, otherwise PRBS_ERR will remain "1." PRBSCLR shares pin F11 with RLOOPS. Serial Remote Line Loopback (RLOOPS) is disabled when PRBS_EN is enabled.
17
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
2.0 RECEIVE SECTION The receive section of XRT91L82 includes the differential inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high-speed Non-Return to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential input interfaces RXIP/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered serial data is converted into 16-bit-wide 155.52/166.63 Mbps parallel data and presented to the RXDO[15:0]P/N parallel interface. This parallel interface can be configured for Differential LVPECL/LVDS, or Single-Ended LVPECL operation. A divide-by-16 version of the high-speed recovered clock, RXPCLKOP/N is used to synchronize the transfer of the 16-bit RXDO[15:0]P/N data with the receive portion of the upstream device. Upon initialization or loss of signal or loss of lock the 155.52 MHz or 166.63 MHz external local reference clock is used to start-up the clock recovery phase-locked loop for proper operation. In Host Mode, a special loopback feature can be configured when parallel remote loopback (RLOOPP) is used in conjunction with de-jittered loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore jitter generation specifications. 2.1 Receive Serial Input The receive serial CML inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an optical module or an electrical interface. A simplified AC coupled block diagram is shown in Figure 4. FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK
0.1F RXIP RXIN 0.1F XRT91L82 STS-48/ STM-16 Transceiver Optical Module Optical Fiber
NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors are not necessary and can be excluded.
The 2.488/2.666 Gbps high-speed differential CML RXIP/N input swing characteristics is shown in Table 4. Figure 17, "CML Differential Voltage Swing," on page 29 shows the CML differential voltage swing. TABLE 4: DIFFERENTIAL CML INPUT SWING PARAMETERS
PARAMETER VINDIFF VINSE VINBIAS RDIFF DESCRIPTION Differential Input Voltage Swing Single-Ended Input Voltage Swing Input Bias Range (AC Coupled) Differential Input Resistance MIN 100 50 VDD_CML - 0.4 80 100 TYP MAX 2000 1000 VDD_CML - 0.2 120 UNITS mV mV V
18
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.2 External Receive Loop Filter Capacitors
xr
REV. P1.0.5
These external loop filter 0 resistors and 22F non-polarized capacitor provide the necessary components to achieve the required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block. Figure 5 shows the pin connections and external loop filter components. The external loop filter is not needed while in host mode and RXCAP1N becomes the charge pump output for the external VCXO. FIGURE 5. EXTERNAL LOOP FILTER
0
pin E1
22uF
non-polarized
0 RXCAP1N
CP_OUT (HOST)
RXCAP1P
pin F1
2.3
Receive Clock and Data Recovery
The clock and data recovery unit accepts the high-speed NRZ serial data from the differential CML receiver and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes REF1CLKP/N and/or REF2CLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the local reference clock within 500 ppm. Once this is achieved, the PLL then attempts to lock onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock. When this condition occurs the PLL will declare Loss of Lock and the LOCKDET_CDR signal will be pulled "Low." Whenever a Loss of Lock/Loss of Signal Detection (LOSD) event occurs, the CDR will continue to supply a receive clock (based on the local reference clock) to the upstream framer device. A Loss of Lock condition will also be declared when the external SDEXT becomes inactive. When the SDEXT is de-asserted by the optical module or when DISRD is asynchronously asserted "Low," receive parallel data output will be forced to a logic zero state for the entire duration that a LOSD condition is detected or for as long as DISRD is asserted "Low." This acts as a receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming data. When the SDEXT becomes active and the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source, the clock recovery PLL will switch and lock back onto the incoming receive data stream and the lock detect output (LOCKDET_CDR) will go active. Table 5 specifies the Clock and Data Recovery Unit performance characteristics.
19
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 5: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
NAME
REFDUTY REFTOL OCLKJIT OCLKJIT TOLJIT OCLKFREQ OCLKDUTY Reference clock duty cycle
PARAMETER
MIN
45 -20
TYP
MAX
55 +20
UNITS
% ppm mUIrms mUIrms UI GHz %
Reference clock frequency tolerance1 Clock output jitter generation with 155.52 MHz reference clock Clock output jitter generation with 166.63 MHz reference clock Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern Frequency output Clock output duty cycle
5 5 0.4 2.488 45
7 7 0.7 2.667 55
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1
Required to meet SONET output frequency stability requirements.
2.4
External Signal Detection
XRT91L82 supports external Signal Detection (SDEXT). The external Signal Detect function is supported by the SDEXT input. This input is coming from the optical module through an output usually called "SD" or "FLAG" which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The SDEXT and POLARITY inputs are Exclusive OR'ed to generate the internal Loss of Signal Detect (LOSD) declaration and Mute upon LOSD control signal. Whenever an external SD is absent, the XRT91L82 will automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOSD condition is declared as well as update the status registers whenever the host mode serial microprocessor interface feature is active. This acts as a receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming data. Table 6 specifies SDEXT declaration polarity settings. TABLE 6: LOSD DECLARATION POLARITY SETTING
SDEXT
0
POLARITY INTERNAL SIGNAL DETECT
0 Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. LOSD not declared. Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. LOSD declared. Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. LOSD declared. Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. LOSD not declared.
RECEIVE PARALLEL DATA OUTPUT RXDO[15:0]P/N
Not Muted
CLOCK AND DATA RECOVERY PLL REFERENCE LOCK
Hi-Spd Received Data
0
1
Muted
Local Reference Clock
1
0
Muted
Local Reference Clock
1
1
Not Muted
Hi-Spd Received Data
20
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 2.5 Receive Serial Input to Parallel Output (SIPO)
xr
REV. P1.0.5
The SIPO is used to convert the 2.488/2.666 Gbps serial data input to 155.52/166.63 Mbps parallel data output which can interface to a SONET Framer/ASIC. The SIPO bit de-interleaves the serial data input into a 16-bit parallel output to RXDO[15:0]P/N. A simplified block diagram is shown in Figure 6. FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF SIPO
16-bit Parallel Data Output RXDO0P/N b03 b02 b01 b00
time (0) 2.488/2.666 Gbps SIPO b153 b143 b133 b123 b113 b103 b93 b70 b60 b50 b40 b30 b20 b10 b00 RXIP/N
RXDOnP/N
bn3 bn2 bn1 bn0
RXDOn+P/N
bn+3 bn+2 bn+1 bn+0
RXDO15P/N
b153 b152 b151 b150
RXPCLKOP/N
155.52/ 166.63 MHz
2.6
Receive Parallel Output Interface
The 16-bit LVDS, Differential LVPECL or Single-Ended LVPECL 155.52/166.63 Mbps parallel data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered clock. A simplified block diagram is shown in Figure 7. FIGURE 7. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
RXDO[15:0]P/N
16
RXPCLKOP/N
XRT91L82 STS-48/STM-16 Transceiver
SONET Framer/ASIC
DISRD DISRDCLK
SDEXT POLARITY
21
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
2.7
Receive Parallel Interface LVDS Operation
When operating the 16-bit Differential bus in LVDS mode, a 402 external resistor is needed across XRES1P and XRES1N to properly bias the RXDO[15:0]P/N and RXPCLKOP/N pins. Figure 8 shows the proper biasing resistor installed. FIGURE 8. LVDS EXTERNAL BIASING RESISTORS
402
+/- 1 % tolerance
pin E14
XRES1P
XRES1N
pin F14
2.8
Parallel Receive Data Output Disable/Mute Upon LOSD
The parallel receiver data outputs are automatically pulled "Low" during a LOSD condition to prevent data chattering. However, the user must select the proper SDEXT polarity for the optical module used. In addition, by pulling DISRD "Low", the receiver data outputs will be muted asynchronously or forced to a logic state of "0" regardless of the data input stream. 2.9 Parallel Receive Clock Output Disable Like DISRD, DISRDCLK is used to mute the parallel receiver clock output RXPCLKOP/N regardless of the data input stream. By pulling DISRDCLK "Low", the receiver clock output will be asynchronously muted whenever desired. 2.10 Receive Parallel Data Output Timing The receive parallel data output from the STS-48/STM-16 receiver will adhere to the setup and hold times shown in Figure 9 and Table 7. FIGURE 9. RECEIVE PARALLEL OUTPUT TIMING
RXPCLKOP/N tRX_INV RXDO[15:0]P/N tRX_DEL
tRXPCLKO tRX_INV
SAMPLE WINDOW
tRX_DEL
TABLE 7: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS
SYMBOL
tRXPCLKO tRXPCLKO tRX_INV tRX_DEL RXDUTY
PARAMETER
Receive parallel clock output period (155.52 MHz non-FEC rate) Receive parallel clock output period (166.63 MHz FEC rate) RXPCLKOP/N "Low" to data invalid window RXPCLKOP/N "Low" to data delay RXPCLKOP/N Duty Cycle
MIN
TYP
6.43 6.00
MAX
UNITS
ns ns
1000 900 45 55
ps ps %
22
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION
xr
REV. P1.0.5
The transmit section of the XRT91L82 accepts 16-bit parallel data and converts it to serial CML data output intented to interface to an optical module. It consists of a 16-bit parallel Differential LVPECL/LVDS, or SingleEnded LVPECL interface, a 16x9 FIFO, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current Mode Logic (CML) differential line driver, and Loop Timing modes. The CML serial data output rate is 2.488/ 2.666 Gbps for STS-48 applications. The high frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In order to synchronize the data transfer process, the synthesized 2.488/2.666 GHz serial clock output is divided by sixteen and the 155.52/166.63 MHz clock is presented to the upstream device to be used as its timing source. 3.1 Transmit Parallel Interface The parallel data from an upstream device is presented to the XRT91L82 through a 16-bit Differential LVPECL/ LVDS/Single-Ended LVPECL parallel bus interface TXDI[15:0]P/N. The data is latched into a parallel input register on the rising edge of TXPCLKIP/N. If the SONET Framer/ASIC is synchronized to the same timing source as the XRT91L82, the transmit data and clock input can directly interface to the STS-48/STM-16 transceiver. However, if the SONET Framer/ASIC is synchronized to a separate crystal, the XRT91L82 has two clock output references that can be used to synchronize the SONET Framer/ASIC. TXPCLKOP/N is a 155.52/166.63 MHz Differential LVPECL/LVDS or Single-Ended LVPECL clock output source that is derived from the CMU synthesized clock. TXCLKO16P/N is a 155.52/166.63 MHz or 19.44/20.83 MHz Differential LVPECL/LVDS or Single-Ended LVPECL auxiliary clock output source that is also derived from the CMU sythensized clock. Either of these two clock output sources can be used to synchronize the SONET Framer/ ASIC to the XRT91L82. A simplified block diagram of the parallel interface is shown in Figure 10. FIGURE 10. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
TXDI[15:0]P/N
16
TXPCLKIP/N
XRT91L82 STS-48/STM-16 Transceiver
TXPCLKOP/N
SONET Framer/ASIC
TXCLKO16P/N TXCLKO16SEL
23
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3.2
Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 11 and Table 8. Table 9 shows the parameters for TXPCLKOP/N clock output. FIGURE 11. TRANSMIT PARALLEL INPUT TIMING
TXPCLKOP/N
tTXPCLKO
TXPCLKIP/N tTXDI_SU TXDI[15:0]P/N tTXDI_HD
tTXPCLKI
TABLE 8: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION
SYMBOL
tTXPCLKI tTXPCLKI tTXDI_SU tTXDI_HD TXDUTY
PARAMETER
Transmit parallel clock input period (155.52 MHz non-FEC rate) Transmit parallel clock input period (166.63 MHz FEC rate) TXPCLKIP/N "High" to data setup time TXPCLKIP/N "High" to data hold time TXPCLKIP/N Duty Cycle
MIN
TYP
6.43 6.00
MAX
UNITS
ns ns ps ps
1000 500 40 60
%
TABLE 9: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION
SYMBOL
tTXPCLKO tTXPCLKO TXDUTY
PARAMETER
Transmit parallel clock output period (155.52 MHz non-FEC rate) Transmit parallel clock output period (166.63 MHz FEC rate) TXPCLKOP/N Duty Cycle
MIN
TYP
6.43 6.00
MAX
UNITS
ns ns
45
55
%
3.3
Transmit FIFO
The Parallel Interface also includes a 16x9 FIFO that can be used to eliminate difficult timing issues between the input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed clock. Should the delay exceed this amount, the read and write pointers will point to the same word in the FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET signal.
24
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.0.5
In Host Mode, the transceiver under the control of the FIFO_AUTORST register bit can automatically recover from an overflow condition. When the FIFO_AUTORST register bit is set to a "High" level, once an overflow condition is detected, the chip will set the OVERFLOW pin to a high level and will automatically reset and center the FIFO. Figure 12 provides a detailed overview of the transmit FIFO in a system interface. FIGURE 12. TRANSMIT FIFO AND SYSTEM INTERFACE
Upstream Device
OVERFLOW RESET TXPCLKIP/N
FIFO_AUTORST(Host Mode)
XRT91L82
delay
16 x 9 FIFO
Write Pointer
TXDI[15:0]P/N
16
Read Pointer TXPCLKOP/N
16
FIFO Control
Div by 16 2.488/2.666 GHz PLL CMU
REF1CLKP/N REF2CLKP/N
3.4
FIFO Calibration Upon Power Up
It is required that the FIFO_RST pin be pulled "High" for 2 TXPCLKOP/N cycles to flush out the FIFO after the device is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually reset the FIFO. In Host Mode, the STS-48 transceiver has an automatic FIFO reset register bit that will allow the FIFO to automatically reset upon an Overflow condition. FIFO_AUTORST register bit should be pulled "High" to enable the automatic FIFO reset function. 3.5 Transmit Parallel Input to Serial Output (PISO) The PISO is used to convert 155.52/166.63 Mbps parallel data input to 2.488/2.666 Gbps serial data output which can interface to an optical module. The PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI15P/N, then the first bit from TXDI14P/N, and so on as shown in Figure 13. FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO
16-bit Parallel DIFF Input Data TXDI0P/N b07 b06 b05 b04 b03 b02 b01 b00 time (0) TXDInP/N bn7 bn6 bn5 bn4 bn3 bn2 bn1 bn0 2.488/ 2.666 Gbps PISO b150 b140 b130 b120 b110 b100 b77 b67 b57 b47 b37 b27 b17 b07 TXOP/N
TXDIn+P/N
bn+7 bn+6 bn+5 bn+4 bn+3 bn+2 bn+1 bn+0
TXDI15P/N
b157 b156 b155 b154 b153 b152 b151 b150
TXPCLKIP/N
155.52/ 166.63 MHz
25
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3.6
Clock Multiplier Unit (CMU) and Re-Timer
The high-speed serial clock synthesized by the CMU is divided by 16 and is then presented to the upstream device as TXPCLKOP/N clock. The upstream device should use TXPCLKOP/N as its timing source. The upstream device then generates the TXPCLKIP/N clock that is phase aligned with the transmit data and provides it to the parallel interface of the transmitter. The data must meet setup and hold times with respect to TXPCLKIP/N. The XRT91L82 will latch TXDI[15:0]P/N on the rising edge of TXPCLKIP/N. The clock synthesizer uses a PLL to lock to the differential input reference clock REF1CLKP/N and REF2CLKP/N. REF1CLKP/N and/or REF2CLKP/N input can accept a clock from a Differential LVPECL crystal oscillator that has a frequency accuracy better than 20ppm in order for the TXSCLKOP/N frequency to have the accuracy required for SONET systems. It will then use this reference clock to generate the 2.488/2.666 GHz STS-48/ STM-16 serial clock output TXSCLKOP/N and in addition feed this high-speed synthesized clock to the PISO. The Retimer will then align the transmit serial data from the PISO with this 2.488/2.666 GHz synthesized clock to generate the output TXOP/N. Table 10 specifies the Clock Multiplier Unit performance characteristics. In Host Mode, the clock synthesizer can also be driven by an optional external VCXO for loop timed or local reference de-jitter applications. VCXO_IN can be connected to the output of a VCXO that can be configured to clean up the recovered received clock coming from CP_OUT in loop timing mode before being applied to the input of the transmit CMU as a reference clock. In addition, the internal phase/frequency detector and charge pump, combined with an external VCXO can alternately be used as a jitter attenuator to de-jitter a noisy system reference clock such as REF1CLKP/N or REF2CLKP/N prior to it being used to time the CMU. The following Section 3.7, "Loop Timing and Clock Control," on page 26 illustrate the use of this method. TABLE 10: CLOCK MULTIPLIER UNIT PERFORMANCE
NAME
REFDUTY REFTOL REFSTS48 OCLKJIT OCLKJIT OCLKFREQ OCLKDUTY
PARAMETER
Reference clock duty cycle Reference clock frequency tolerance1 Reference clock jitter limits from 12 KHz to 20 MHz Clock output jitter generation with 155.52 MHz reference clock Clock output jitter generation with 166.63 MHz reference clock Frequency output Clock output duty cycle
MIN
45 -20
TYP
MAX
55 +20 -61
UNITS
% ppm dBC mUIrms mUIrms GHz %
3.2 3.2 2.488 45
5.0 5.0 2.667 55
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1
Required to meet SONET output frequency stability requirements.
3.7
Loop Timing and Clock Control
Two types of loop timing are possible in the XRT91L82. In the Hardware mode, the loop timing (without an external VCXO) is controlled by the LOOPTM_NOJA pin. This mode is selected by asserting the LOOPTM_NOJA signal to a "High" level. When the loop timing mode is activated, the external local reference clock to the input of the CMU is replaced with the 1/16th of the highspeed recovered receive clock coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the recovered receive clock. The normal looptime mode directly locks the CMU to the recovered receive clock with no external de-jittering. In Host Mode, loop timing performance can be further improved using an external VCXO-based PLL to clean up the jitter of the recovered receive clock. In this case the VCXO_SEL register bit should be set "High." By doing so, the CMU receives its reference clock signal from an external VCXO connected to the VCXO_IN input. The LOOPTM_JA register bit must also be set "High" in order to select the recovered receive clock as the reference source for the de-jitter PLL. In this state, the VCXO will be phase locked to the recovered receive clock through a narrowband loop filter. The use of the on-chip phase/frequency detector with charge pump and an external VCXO to remove the transmit jitter due to jitter in the recovered clock is shown in Figure 14.
26
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.0.5
The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that is applied to the REF1CLKP/N or REF2CLKP/N inputs. In this case the LOOPTM_NOJA register bit should be set "Low," the VCXO_SEL set "High," and the LOOPTM_JA register bit set "Low." In this configuration, the REF1CLKP/N or REF2CLKP/N CMU reference signal is used as the reference to the de-jitter PLL and the dejittered output of the phase locked VCXO is used as the timing reference to the CMU. Table 11 provides configuration for selecting the loop timing and reference de-jitter modes. TABLE 11: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS
VCXO_SEL (REGISTER BIT) 0 0 1 LOOPTM_JA (REGISTER BIT) 0 0 0 LOOPTM_NOJA (PIN/REGISTER BIT) 0 1 0 CONFIGURATION
HARDWARE AND HOST MODE HARDWARE AND HOST MODE HOST MODE ONLY
ACTION
Normal mode Loop timing without de-jitter VCXO REF1CLKP/N or REF2CLKP/N reference de-jitter VCXO Loop timing with de-jitter VCXO
1
1
0
HOST MODE ONLY
FIGURE 14. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO (HOST MODE ONLY)
VCXO
Loop Filter
LOOPTM_JA Serial Microprocessor VCXO_SEL LOOPTM_NOJA REF1CLKP REF1CLKN REF2CLKP REF2CLKN VCXO_IN 1 REFREQSEL1 REFREQSEL0 HOST/ HW LOCKDET_CMU ALTFREQSEL MUX 1 0 MUX Phase Detect Charge Pump RXCAP1N/ CPOUT
MUX
0
MUX
0 2.488/2.666GHz CMU PISO 2.488/2.666GHz Retimer TXOP TXON
1 MUX LOOPTM_NOJA
Div by 16 or 32
Clk CDR Data
RXIP RXIN
~
XRT91L82
~
27
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3.8
External Loop Filter (Host Mode Only)
During Host Mode operation, RXCAP1N becomes the charge pump output CP_OUT. As shown in Figure 14, the internal charge pump is used to drive an external loop filter and external VCXO. The charge pump current is fixed at 250uA. Figure 15 is a simplified block diagram of the external loop filter and recommended values. FIGURE 15. SIMPLIFIED DIAGRAM OF THE EXTERNAL LOOP FILTER
CPOUT VCXO 4.02k 300pF 1uF
3.9
Transmit Serial Output Control
The 2.488/2.666 Gbps transmit serial output is avaliable on TXOP/N pins. The transmit serial output can be AC or DC coupled to an optical module or electrical interface. A simplified AC coupling block diagram is shown in Figure 16. FIGURE 16. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK
0.1F TXOP TXON 0.1F XRT91L82 STS-48/ STM-16 Transceiver Optical Module Optical Fiber
NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors are not necessary and can be excluded.
The 2.488/2.666 Gbps high-speed differential CML output TXOP/N swing mode can be controlled through an pin called TXSWING. Setting this pin "Low" enables Low Swing Mode and lowers power consumption. Setting this pin "High" configures the transmit serial output for High Swing Mode. Figure 17 shows the CML differential voltage swing. TABLE 12: DIFFERENTIAL CML OUTPUT SWING PARAMETERS
SIGNAL TYPE
Clock Clock Data Data
PARAMETER
VOUTDIFF VOUTSE VOUTDIFF VOUTSE
MIN (mV)
700 350 800 400
MAX (mV)
1400 700 1400 700
CML SERIAL VOLTAGE OUTPUT
Differential Voltage Swing Single-Ended Voltage Swing Differential Voltage Swing Single-Ended Voltage Swing
TXSWING SETTING (100 LINE TO LINE)
High Swing Mode High Swing Mode High Swing Mode High Swing Mode
28
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 12: DIFFERENTIAL CML OUTPUT SWING PARAMETERS
SIGNAL TYPE
Clock Clock Data Data
xr
REV. P1.0.5
PARAMETER
VOUTDIFF VOUTSE VOUTDIFF VOUTSE
MIN (mV)
400 200 400 200
MAX (mV)
700 350 850 425
CML SERIAL VOLTAGE OUTPUT
Differential Voltage Swing Single-Ended Voltage Swing Differential Voltage Swing Single-Ended Voltage Swing
TXSWING SETTING (100 LINE TO LINE)
Low Swing Mode Low Swing Mode Low Swing Mode Low Swing Mode
FIGURE 17. CML DIFFERENTIAL VOLTAGE SWING
V(+)
VSINGLE
V(-) V(+) - V(-)
VDIFF = 2X VSINGLE
0V
29
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback
RLOOPS_PRBSCLR is a dual function pin that serves as both serial remote loopback enable and PRBS error clear function. The serial remote loopback function is activated by setting RLOOPS_PRBSCLR "Low". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at the highspeed transmit output TXOP/N, and the high-speed recovered clock is selected and presented to the highspeed transmit clock output TXSCLKOP/N. During serial remote loopback, the high-speed receive data (RXIP/ N) is also converted to parallel data and presented at the low-speed receive parallel interface RXDO[15:0]P/N. The recovered receive clock is also divided by 16 and presented at the low-speed clock output RXPCLKOP/N to synchronize the transfer of the 16-bit received parallel data. In PRBS Test Mode, serial remote loopback is not available when the PRBS generator and analyzer is enabled. This pin serve as the PRBS error clear (PRBSCLR) function to reset the PRBS_ERR error output indicator. A simplified block diagram of serial remote loopback is shown in Figure 18.
FIGURE 18. SERIAL REMOTE LOOPBACK
Serial Remote Loopback CML Output Drivers
FIFO
PISO
Re-Timer
TX Serial Output
RX Parallel Output
SIPO
CDR
CML Input Drivers
RX Serial Input
4.2
Parallel Remote Loopback (Host Mode Only)
RLOOPP controls a more comprehensive version of remote loopback that can also be used in conjunction with the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is processed by the CDR, and is sent through the serial to parallel converter. At this point, the 16-bit parallel data and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also employed, the received clock is divided down in frequency and presented to the input of the integrated phase/ frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_IN input. With the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL asserted, the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime the transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset using FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified block diagram of parallel remote loopback is shown in Figure 19.
FIGURE 19. PARALLEL REMOTE LOOPBACK
Parallel Remote Loopback CML Output Drivers
FIFO
PISO
Re-Timer
TX Serial Output
RX Parallel Output
SIPO
CDR
CML Input MUX
RX Serial Input
30
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 4.3 Digital Local Loopback
xr
REV. P1.0.5
The digital local loopback is activated when the DLOOP signal is set "Low." When digital local loopback is activated, the high-speed data from the output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. The CMU output is also looped back to the receive section and is used to synchronize the transfer of the data through the receiver. In Digital loopback mode the transmit data from the transmit parallel interface TXDI[15:0]P/N is serialized and presented to the high-speed transmit output TXOP/N along with the high-speed transmit clock which is generated from the clock multiplier unit and presented to the TXSCLKOP/N pins. A simplified block diagram of digital loopback is shown in Figure 20.
FIGURE 20. DIGITAL LOOPBACK
Digital Loopback CML Output Drivers
TX Parallel Input
FIFO
PISO
Re-Timer
TX Serial Output
RX Parallel Output
SIPO
CDR
CML Input Drivers
31
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
4.4
SONET Jitter Requirements
SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are specified for the following three types of jitter.
4.4.1 Jitter Tolerance:
Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input OC-N equipment interface that causes an equivalent 1dB optical power penalty. OC-1/STS-1, OC-3/STS-3, OC-12/ STS-12 and OC-48/STS-48 category II SONET interfaces should tolerate, the input jitter applied according to the mask of Figure 21, with the corresponding parameters specified in the figure.
FIGURE 21. JITTER TOLERANCE MASK
A3 slope= -20dB/decade Input Jitter Amplitude (UIpp) slope= -20dB/decade A2
A1
f0
f1
f2
f3
f4
Jitter Frequency (Hz)
OC-N/STS-N LEVEL 1 3 12 48
F0 (HZ) 10 10 10 10
F1 (HZ) 30 30 30 600
F2 (HZ) 300 300 300 6000
F3 (HZ) 2K 6.5K 25K 100K
F4 (HZ) 20K 65K 250K 1000K
A1 (UIPP) 0.15 0.15 0.15 0.15
A2 (UIPP) 1.5 1.5 1.5 1.5
A3 (UIPP) 15 15 15 15
32
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.0.5
FIGURE 22. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16
TBD
FIGURE 23. XRT91L82 MEASURED JITTER TOLERANCE IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE
TBD
4.4.2
Jitter Transfer
Jitter transfer is defined as the ratio of the jitter on the output of STS-N to the jitter applied on the input of STS-N versus frequency. Jitter transfer is important in applications where the system is utilized in the looptimed mode, where the recovered clock is used as the source of the transmit clock.
FIGURE 24. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.488 GBPS STS-48/STM-16
TBD
FIGURE 25. XRT91L82 MEASURED JITTER TRANSFER IN LOOP TIMING MODE AT 2.666 GBPS FEC MODE
TBD
33
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
4.4.3
Jitter Generation
Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The Bellcore and ITU requirement for this type jitter is 0.01UI rms measured with a specific band-pass filter. For more information on these specifications refer to Bellcore TR-NWT-000253 sections 5.6.2-5 and GR-253CORE section 5.6.
FIGURE 26. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.488 GBPS
TBD
FIGURE 27. XRT91L82 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 2.666 GBPS
TBD
34
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK
xr
REV. P1.0.5
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the transceiver. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by pulling reset "Low" for more than 30ns. A simplified block diagram of the Serial Microprocessor is shown in Figure 28.
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
CS SCLK SDI
SDO INT
Serial Microprocessor Interface
HW/Host
RESET
5.1 SERIAL TIMING INFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 29.
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
CS
25nS 50nS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
R/W
A0
A1
A2
A3
A4
A5
X
D0
D1
D2
D3
D4
D5
D6
D7
SDO
High-Z
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active "Low") must be de-asserted at the end of every single write or single read operation.
35
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION
The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is updated on the falling edge of SCLK. The serial data must be applied to the transceiver LSB first. The 16 bits of serial data are described below.
5.2.1 R/W (SCLK1)
The first serial bit applied to the transceiver informs the microprocessor that a Read or Write operation is desired. If the R/W bit is set to "0", the microprocessor is configured for a Write operation. If the R/W bit is set to "1", the microprocessor is configured for a Read operation.
5.2.2 A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0 (LSB) must be sent to the transceiver first followed by A1 and so forth until all 6 address bits have been sampled by SCLK.
5.2.3 X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data if the readback mode is selected by setting R/W = "1". Therefore, the state of this bit is ignored and can hold either "0" or "1" during both Read and Write operations.
5.2.4 D[7:0] (SCLK9 - SCLK16) The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the address bits. D0 (LSB) must be sent to the transceiver first followed by D1 and so forth until all 8 data bits have been sampled by SCLK. Once 16 SCLK cycles have been complete, the transceiver holds the data until CS is pulled "High" whereby, the serial microprocessor latches the data into the selected internal register. 5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to "1". D0 (LSB) is provided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The SDO pin allows the user to read the contents stored in individual registers by providing the desired address on the SDI pin during the Read cycle.
36
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER 6.0 REGISTER MAP AND BIT DESCRIPTIONS TABLE 13: MICROPROCESSOR REGISTER MAP
REG ADDR TYPE D7 D6 D5 D4 D3 D2
xr
REV. P1.0.5
D1
D0
Control Registers (0x00h - 0x3Fh)
0 1 2 3 0x00 0x01 0x02 0x03 R/W RUR RO R/W Reserved Reserved Reserved Reserved PRBSLIE PRBSLIS PRBS_LOCK Reserved PRBSEIE PRBSEIS PRBS_ERR Reserved VCXOIE VCXOIS VCXOD Reserved LOSIE LOSIS LOSD Reserved CDRIE CDRIS CDRD Reserved CMUIE CMUIS CMUD FIFO_AUTORST TXSCLKOFF RLOOPS FIFOIE FIFOIS FIFOD FIFO_RST
4 5
0x04 0x05
R/W R/W
Reserved Reserved
Reserved Reserved
Reserved PRBS_INV
Reserved PRBS_EN
DISRD Reserved
DISRDCLK DLOOP
CDRLCKREF RLOOPP
6
0x06
R/W
VCXOLKEN
LOOPBW
Reserved
Reserved
Reserved
VCXO_SEL
LOOPTM_JA
LOOPTM_ NOJA POLARITY
7
0x07
R/W
REFREQSEL 1 Reserved Reserved Reserved Reserved
REFREQSEL ALTFREQSEL 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
TXCLK016 SEL Reserved Reserved Reserved Reserved
INTERM
SEREFDIS
TXSWING
8 9 10 11
0x08 0x09 0x0A 0x0B R/W RO RO RO
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
0x0C - 0x3B 60 61 63 0x3C 0x3D 0x3F
Reserved Device ID MSB (See Bit Description) Device ID LSB (See Bit Description) Revision ID (See Bit Description)
37
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 14: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
INTERRUPT ENABLE CONTROL REGISTER (0X00H)
Register Type Default Value (HW reset) X 0
BIT
NAME
FUNCTION
D7 D6
Reserved PRBSLIE
This Register Bit is Not Used
X R/W
223-1 PRBS Pattern Lock Interrupt Enable "0" = Masks the PRBS Pattern Lock interrupt generation "1" = Enables Interrupt generation NOTE: PRBS_EN must be enabled for this bit to have functional meaning.
D5
PRBSEIE
223-1 PRBS Pattern Error Interrupt Enable "0" = Masks the PRBS error interrupt generation "1" = Enables Interrupt generation NOTE: PRBS_EN must be enabled for this bit to have functional meaning.
R/W
0
D4
VCXOIE
Voltage Controlled External Oscillator Lock Interrupt Enable "0" = Masks the VCXO Lock interrupt generation "1" = Enables Interrupt generation NOTE: VCXOLKEN must be enabled for this bit to have functional meaning.
R/W
0
D3
LOSIE
Loss of Signal Interrupt Enable "0" = Masks the LOS interrupt generation "1" = Enables Interrupt generation Clock and Data Recovery Lock Interrupt Enable "0" = Masks the CDR Lock interrupt generation "1" = Enables Interrupt generation Clock Multiplier Unit Lock Interrupt Enable "0" = Masks the CMU Lock interrupt generation "1" = Enables Interrupt generation FIFO Overflow Interrupt Enable "0" = Masks the FIFO Overflow interrupt generation "1" = Enables Interrupt generation
R/W
0
D2
CDRIE
R/W
0
D1
CMUIE
R/W
0
D0
FIFOIE
R/W
0
38
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 15: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
INTERRUPT STATUS CONTROL REGISTER (0X01H)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) X 0
D7 D6
Reserved PRBSLIS
This Register Bit is Not Used
X RUR
223-1 PRBS Pattern Lock Interrupt Status An external interrupt will not occur unless the PRBSLIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in PRBS Lock Status Occurred NOTE: PRBS_EN must be enabled for this bit to have functional meaning.
D5
PRBSEIS
223-1 PRBS Pattern Error Detect Interrupt Status Indicates an error condition has occurred in the validation of generated PRBS pattern. "0" = Un-erred transmission and reception of PRBS pattern. "1" = PRBS pattern validation error has Occured NOTE: PRBS_EN must be enabled for this bit to have functional meaning.
RUR
0
D4
VCXOIS
Voltage Controlled External Oscillator Lock Interrupt Status An external interrupt will not occur unless the VCXOIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in VCXO Lock Status Occurred NOTE: VCXOLKEN must be enabled for this bit to have functional meaning.
RUR
0
D3
LOSIS
Loss of Signal Interrupt Status An external interrupt will not occur unless the RLOSIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in LOS Status Occurred Clock and Data Recovery Lock Interrupt Status An external interrupt will not occur unless the CDRIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in CDR Lock Status Occurred Clock Multiplier Unit Lock Interrupt Status An external interrupt will not occur unless the CMUIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in CMU Lock Status Occurred FIFO Overflow Interrupt Status An external interrupt will not occur unless the FIFOIE is set to "1" in the channel register 0x00h. "0" = No Change "1" = Change in FIFO Overflow Status Occurred
RUR
0
D2
CDRIS
RUR
0
D1
CMUIS
RUR
0
D0
FIFOIS
RUR
0
39
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 16: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
STATUS CONTROL REGISTER (0X02H)
Register Type Default Value (HW reset) X 0
BIT
NAME
FUNCTION
D7 D6
Reserved
This Register Bit is Not Used
X RO
PRBS_LOCK 223-1 PRBS Pattern Lock Detection Indicates that current state condition of the PRBS pattern analyzer when the PRBS pattern generator is enabled. "0" = PRBS pattern analyzer currently Out of Lock "1" = PRBS pattern analyzer currently Locked PRBS_ERR 223-1 PRBS Pattern Error Detection Indicates an error condition is occuring in the validation of generated PRBS pattern. "0" = Un-erred transmission and reception of PRBS pattern. "1" = PRBS pattern validation error condition is present.
D5
RO
0
NOTE: PRBS_EN must be enabled for this bit to have functional meaning.
D4 VCXOD
Voltage Controlled External Oscillator Lock Detection The VCXOD is used to indicate whether the internal clock reference is locked to an external VCO. "0" = VCXO currently not Locked "1" = VCXO Locked NOTE: VCXOLKEN must be enabled for this bit to have functional meaning.
RO
0
D3
LOSD
Loss of Signal Detection The LOSD indicates the Loss of Signal Detect activity. "0" = No Alarm "1" = A LOSD condition is present Clock and Data Recovery Lock Detection The CDRD is used to indicate that the CDR is locked. "0" = CDR Out of Lock "1" = CDR Locked Clock Multiplier Unit Lock Detection The CMUD is used to indicate that the CMU is locked. "0" = CMU Out of Lock "1" = CMU Locked FIFO Overflow Detection The FIFOD indicates that the FIFO is experiencing an overflow condition. "0" = No Alarm "1" = A FIFO Overflow condition is present
RO
0
D2
CDRD
RO
0
D1
CMUD
RO
0
D0
FIFOD
RO
0
40
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 17: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
FIFO CONTROL REGISTER (0X03H)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) X X X X X X 0
D7 D6 D5 D4 D3 D2 D1
Reserved Reserved Reserved Reserved Reserved Reserved FIFO_ AUTORST
This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used
X X X X X X R/W
Automatic FIFO Overflow Reset If this bit is set to "1", the STS-48 transceiver will automatically flush the FIFO upon an overflow condition. Upon power-up, the FIFO should be manually reset by setting FIFO_RST to "1" for a minimum of 2 TXPCLKOP/N cycles. "0" = Manual FIFO reset required for Overflow Conditions "1" = Automatically resets FIFO upon Overflow Detection Manual FIFO Reset FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N cycles during power-up and manual FIFO reset in order to flush out the FIFO. After the FIFORST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an interrupt indication that the FIFO has an overflow condition, this bit is used to reset or flush out the FIFO. "0" = Normal Operation "1" = Manual FIFO Reset NOTE: To automatically reset the FIFO, see the FIFO_AUTORST bit.
D0
FIFO_RST
R/W
0
41
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 18: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
OUTPUT CONTROL REGISTER (0X04H)
Register Type Default Value (HW reset) X X X X 1
BIT
NAME
FUNCTION
D7 D6 D5 D4 D3
Reserved Reserved Reserved Reserved DISRD
This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used
X X X X R/W
Receive Parallel Data Output Disable If this bit is set to "0", the 16-bit parallel receive data output will asynchronously mute. "0" = Forces RXDO[15:0]P/N to a logic state "0" "1" = Normal Mode Receive Parallel Clock Output Disable This bit is used to asynchronously control the activity of the parallel receive clock output. "0" = Forces RXPCLKOP/N to a logic state of "0" "1" = Normal Mode Transmit Serial Clock Output Tristate This bit is used to control the activity of the 2.488/2.666 GHz differential serial clock output. Tristating TXSCLKOP/N output reduces power consumption. "0" = TXSCLKOP/N output Enabled "1" = TXSCLKOP/N output Tristated CDR's Recovered High-speed Serial Clock Reference Controls CDR's operation. "0" = Forced to lock to CDR PLL reference training clock "1" = Normal Operation (Locked to incoming serial data)
D2
DISRDCLK
R/W
1
D1
TXSCLKOOFF
R/W
1
D0
CDRLCKREF
R/W
1
42
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 19: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
DIAGNOSTIC CONTROL REGISTER (0X05H)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) X X 0
D7 D6 D5
Reserved Reserved
This Register Bit is Not Used This Register Bit is Not Used
X X R/W
PRBS_INV 223-1 PRBS Pattern Invert This bit will invert each of the Pseudo Random Binary Sequence pattern bit from "0" to "1" and from "1" to "0." "0" = Normal Operation "1" = PRBS bit patterns inverted. PRBS_EN
D4
223-1 PRBS TEST Pattern Enable
Generates Pseudo Random Binary Sequence test patterns and analyzes in the receiving block for correct sequence pattern. "0" = Normal Mode "1" = PRBS pattern generator and analyzer Enabled. 223-1
R/W
0
NOTE:
A Local Loopback of some type such as Digital Local Loopback or an optical cable loopback is expected to be used in conjunction with PRBS_EN in order for the PRBS analyzer to receive the PRBS pattern.
X R/W X 1
D3 D2
Reserved DLOOP
This Register Bit is Not Used
Digital Local Loopback Digital local loopback allows the transmit input pins to be looped back to the receive output pins for local diagnostics. The transmit serial data output is valid during the digital loopback. "0" = Enable Digital Local Loopback "1" = Disabled NOTE: RLOOPS and RLOOPP should be disabled when DLOOP is enabled.
43
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
DIAGNOSTIC CONTROL REGISTER (0X05H)
Register Type Default Value (HW reset) 1
BIT
NAME
FUNCTION
D1
RLOOPS
Serial Remote Loopback Serial remote loopback allows the receive serial input pins to be looped back to the transmit serial output pins for remote diagnostics. The receive data output is valid during a serial remote loopback. "0" = Enable Remote Serial Loopback "1" = Disabled NOTE: DLOOP and RLOOPP should be disabled when RLOOPS is enabled.
R/W
D0
RLOOPP
Parallel Remote Loopback Parallel remote loopback has the same affect as the serial remote loopback, except that the data input is allowed to pass through the SIPO before it's looped back to the transmit path, wherein it passes through the transmit FIFO, through the PISO, and back out the transmit serial output. The receive data output is valid during a parallel remote loopback. "0" = Enable Remote Parallel Loopback "1" = Disabled NOTE: DLOOP and RLOOPS should be disabled when RLOOPP is enabled. The internal FIFO should also be flushed using FIFO_RST when parallel remote loopback is enabled/ disabled.
R/W
1
44
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 20: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
TIMING CONTROL REGISTER (0X06H)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) 0
D7
VCXOLKEN
De-Jitter PLL Lock Detect Enable This bit enables the VCXO_IN input lock detect circuit to be active. "0" = VCXO Lock Detect Disabled "1" = VCXO Lock Detect Enabled CMU Loop Band Width Select This bit is used to select the bandwidth of the clock multiplier unit of the transmit path to a narrow or wide band. Use Wide Band for clean reference signals and Narrow Band for noisy references. "0" = Wide Band (4x) "1" = Narrow Band (1x)
This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used
R/W
D6
LOOPBW
R/W
0
D5 D4 D3 D2
Reserved Reserved Reserved VCXO_SEL
X X X R/W
X X X 0
VCXO De-Jitter Select This bit selects either the normal REF1CLKP/N and REF2CLKP/N or the de-jitter VCXO_IN as a reference clock to the CMU. "0" = Normal REF1CLKP/N and/or REF2CLKP/N Mode "1" = De-Jitter VCXO Mode
D1
LOOPTM_JA
Loop Timing With Jitter Attenuation
The LOOPTM_JA bit must be set to "1" in order to select the recovered receive clock as the reference source for the de-jitter PLL. "0" = Disabled "1" = Loop timing with de-jitter PLL Activated
R/W
0
D0
LOOPTM_ NOJA
Loop Timing With No Jitter Attenuation
When the loop timing mode is activated, the external local reference clock input to the CMU is replaced with the 1/16th or 1/32nd (ALTFREQSEL option available in Host Mode) of the high-speed recovered receive clock coming from the CDR. "0" = Disabled "1" = Loop timing Activated
R/W
0
45
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 21: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CONFIGURATION CONTROL REGISTER (0X07H)
Register Type Default Value (HW reset) 0
BIT
NAME
FUNCTION
D7
REFREQSEL1
Input Reference Frequency Select This bit is used to select the clock input reference.
R/W
REFREQSEL [1:0] 00
CMU
REFERENCE FREQUENCY
CDR
REFERENCE FREQUENCY
155.52 MHz present on 155.52 MHz present on REF1CLK REF1CLK REF2CLK not used REF2CLK not used 155.52 MHz present on 166.63 MHz present on REF1CLK REF2CLK 166.63 MHz present on 155.52 MHz present on REF2CLK REF1CLK 166.63 MHz present on 166.63 MHz present on REF2CLK REF2CLK REF1CLK not used REF1CLK not used
01 10 11
Note: Non-FEC transmission and/or reception modes require 155.52 MHz clock reference. FEC transmission and/or reception mode requires 166.63 MHz clock reference. D6 REFREQSEL0
Input Reference Frequency Select This bit is used to select the clock input reference.
R/W
0
REFREQSEL [1:0] 00
CMU
REFERENCE FREQUENCY
CDR
REFERENCE FREQUENCY
155.52 MHz present on 155.52 MHz present on REF1CLK REF1CLK REF2CLK not used REF2CLK not used 155.52 MHz present on 166.63 MHz present on REF1CLK REF2CLK 166.63 MHz present on 155.52 MHz present on REF2CLK REF1CLK 166.63 MHz present on 166.63 MHz present on REF2CLK REF2CLK REF1CLK not used REF1CLK not used
01 10 11
Note: Non-FEC transmission and/or reception modes require 155.52 MHz clock reference. FEC transmission and/or reception mode requires 166.63 MHz clock reference.
46
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
CONFIGURATION CONTROL REGISTER (0X07H)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) 1
D5
ALTFREQSEL
Alternate Low Reference Frequency Select (77.76/83.31 MHz) This pin is used to select and support lower frequency settings on REF1CLKP/N and REF2CLKP/N reference clock inputs. When using a VCXO, this pin should also be set accordingly to the VCXO frequency output. "0" = 77.76/83.31 MHz reference frequency support "1" = 155.52/166.63 MHz reference frequency support
R/W
If ALTFREQSEL = "0"
REFREQSEL [1:0] 00 CMU
REFERENCE FREQUENCY
CDR
REFERENCE FREQUENCY
77.76 MHz present on REF1CLK REF2CLK not used 77.76 MHz present on REF1CLK 83.31 MHz present on REF2CLK 83.31 MHz present on REF2CLK REF1CLK not used
77.76 MHz present on REF1CLK REF2CLK not used 83.31 MHz present on REF2CLK 77.76 MHz present on REF1CLK 83.31 MHz present on REF2CLK REF1CLK not used
01 10 11
Note: Non-FEC transmission and/or reception modes require 77.76 MHz clock reference. FEC transmission and/or reception mode requires 83.31 MHz clock reference.
If ALTFREQSEL = "1"
REFREQSEL [1:0] 00 CMU
REFERENCE FREQUENCY
CDR
REFERENCE FREQUENCY
155.52 MHz present on 155.52 MHz present on REF1CLK REF1CLK REF2CLK not used REF2CLK not used 155.52 MHz present on 166.63 MHz present on REF1CLK REF2CLK 166.63 MHz present on 155.52 MHz present on REF2CLK REF1CLK 166.63 MHz present on 166.63 MHz present on REF2CLK REF2CLK REF1CLK not used REF1CLK not used
01 10 11
Note: Non-FEC transmission and/or reception modes require 155.52 MHz clock reference. FEC transmission and/or reception mode requires 166.63 MHz clock reference. D4 TXCLKO16SEL Auxiliary Clock Output Select This bit is used to select the auxiliary clock frequency output. "0" = TXCLKO16P/N outputs 155.52/166.63 MHz "1" = TXCLKO16P/N outputs 19.44/20.83 MHz R/W 0
47
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
CONFIGURATION CONTROL REGISTER (0X07H)
Register Type Default Value (HW reset) 0
BIT
NAME
FUNCTION
D3
INTERM
Transmit Parallel Bus Input Internal Termination Provides 100 line-to-line internal termination to TXDI[15:0]P/N and TXPCLKIP/N. "Low" = Disabled "High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated. SE_REF Power down Control Powers down SE_REF and reduces power consumption. "0" = SE_REF Enabled "1" = SE_REF Disabled Serial CML Optical Transceiver Swing Select This bit is used to select the output swing of the high-speed CML interface to the optical transceiver. "0" = Low Swing Mode CML Output Selected "1" = High Swing Mode CML Output Selected See Table 12 in "Section 3.9, Transmit Serial Output Control" on page 28. Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT. "0" = SDEXT is active "Low" "1" = SDEXT is active "High"
R/W
D2
SEREFDIS
R/W
1
D1
TXSWING
R/W
1
D0
POLARITY
R/W
1
TABLE 22: MICROPROCESSOR REGISTER 0X3CH BIT DESCRIPTION
DEVICE "ID" REGISTER (0X3CH)
Register Type Default Value (HW reset) 1 0 0 0 0 0 0 0
BIT
NAME
FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Device "ID" The device "ID" of the XRT91L82 LIU is 0x8003h. Along with the revision "ID", the device "ID" is used to enable software to identify MSB the silicon adding flexibility for system control and debug.
RO
48
XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE 23: MICROPROCESSOR REGISTER 0X3DH BIT DESCRIPTION
DEVICE "ID" REGISTER (0X3DH)
xr
REV. P1.0.5
BIT
NAME
FUNCTION
Register Type
Default Value (HW reset) 0 0 0 0 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0
Device "ID" The device "ID" of the XRT91L82 LIU is 0x8003h. Along with the revision "ID", the device "ID" is used to enable software to identify LSB the silicon adding flexibility for system control and debug.
RO
TABLE 24: MICROPROCESSOR REGISTER 0X3FH BIT DESCRIPTION
REVISION "ID" REGISTER (0X3FH)
Register Type Default Value (HW reset) This byte shows the revision of the device.
BIT
NAME
FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Revision "ID"
The revision "ID" of the XRT91L82 LIU is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon (Revision A) will be 0x01h.
RO
49
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
7.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Thermal Resistance of STBGA Package....jA = 25C/W Thermal Resistance of STBGA Package....jC = 10C/W ESD Protection (HBM)..........................................>2000V Operating Temperature Range.................-40 t o 85 C C Case Temperature under bias..................-55 to 125 C C Storage Temperature ...............................-65 to 150 C C
ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS
SYMBOL
VDD1.8 VDD_IO LVPECL LVDS LVTTL/ LVCMOS LVCMOS LVPECL LVTTL/ LVCMOS
TYPE
PARAMETER
1.8V Digital and Analog Power Supplies 3.3V LVPECL/LVDS Input Power Supply DC logic signal input voltage DC logic signal input voltage DC logic signal input voltage
MIN
-0.5 -0.5 -0.5 -0.5 -0.5
TYP
MAX
3.6 6.0 VDD_IO +0.5 VDD_IO +0.5 5.5
UNITS
V V V V V
DC logic signal output voltage Input current Input current
-0.5 -100 -100
VDD_IO +0.5 100 100
V mA mA
NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods will severely affect device reliability.
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS
SYMBOL
VDD1.8 AVDDTX AVDDRX VDD_IO
TYPE
PARAMETER
CML and CMOS Power Supply Voltage Transmit Power Supply Voltage (AVDD_TX) Receiver Power Supply Voltage (AVDD_RX) LVPECL or LVDS Input and Digital I/O Power Supply Voltage 1.8V Power Supply Noise Rejection Ratio 3.3V Power Supply Noise Rejection Ratio
MIN
1.710 1.710 1.710 3.135
TYP
1.8 1.8 1.8 3.3
MAX
1.890 1.890 1.890 3.465 50 50
UNITS
V V V V mVP-P mVP-P mA mA
CONDITIONS
6 KHz 2 MHz 6 KHz 2 MHz
IDD_1.8 IDD_IO
1.8V Total Power Supply Current 3.3V Total Power Supply Current
TBD TBD
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XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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REV. P1.0.5
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS
SYMBOL
PLVDS PLVPECL
TYPE
PARAMETER
Total Power Dissipation Total Power Dissipation
MIN
TYP
500 1400
MAX
700 1700
UNITS
mW mW
CONDITIONS
LVDS LVPECL
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS
Test Condition: TA = 25 VDD 1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5%, VDD_IO= 3.3V + 5% unless otherwise specified C, SYMBOL
VOH VOL VODIFF VOSINGLE VIH VIL VIDIFF
TYPE
LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL
PARAMETER
Output High Voltage Output Low Voltage Output Differential Voltage Swing Output Single-Ended Voltage Swing Input High Voltage Input Low Voltage Input Differential Voltage
MIN
VDD_IO -1.15 VDD_IO -1.95 1 0.5 VDD_IO - 1.2 VDD_IO - 2.0 0.4
TYP
MAX
VDD_IO -0.735 VDD_IO -1.495 2 1 VDD_IO - 0.7 VDD_IO - 1.40 2.4
UNITS
V V V V V V V
CONDITIONS
Single-Ended Differential and Single-Ended Differential and Single-Ended Differential Mode. See Figure 17 Differential Mode. See Figure 17 Single-Ended Mode See Figure 17
VISINGLE
LVPECL
Input Single-Ended Voltage Swing
0.2
1.2
V
VISE
LVPECL
Input Single-Ended Voltage Swing
0.4 (+/- 0.2V w.r.t. VBB100K)
V
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS
Test Condition: TA = 25 VDD 1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified C, SYMBOL
VOH VOL VODIFF VOSINGLE VIH
TYPE
LVDS LVDS LVDS LVDS LVDS
PARAMETER
Output High Voltage Output Low Voltage Output Differential Voltage Swing Output Single-Ended Voltage Swing Input High Voltage
MIN
TYP
MAX
1680
UNITS
mV mV
CONDITIONS
100 line - line 100 line - line 100 line - line 100 line - line
810 450 225 1320 660 2400
mV mV mV
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REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PARAMETER
Input Low Voltage Input Differential Voltage Swing Input Single-Ended Voltage Swing
Test Condition: TA = 25 VDD 1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified C, SYMBOL
VIL VIDIFF VISINGLE
TYPE
LVDS LVDS LVDS
MIN
800 200 100
TYP
MAX
UNITS
mV
CONDITIONS
1300 650
mV mV
LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS
Test Condition: TA = 25 VDD 1.8 = 1.8V + 5%, VDD_IO = 3.3V + 5% unless otherwise specified C, SYMBOL
VOH VOL VIH VIL IIH
TYPE
PARAMETER
MIN
2.93 0 2.2
TYP
MAX
VDD_IO 0.2 3.3
UNITS
V V V
CONDITIONS
IOH = -1.0mA IOH = 1.0mA
LVCMOS Output High Voltage LVCMOS Output Low Voltage LVTTL/ Input High Voltage LVCMOS LVTTL/ Input Low Voltage LVCMOS LVTTL/ Input High Current LVCMOS LVTTL/ Input Low Current LVCMOS LVTTL/ Input Leakage Current LVCMOS LVTTL/ Input Leakage Current with LVCMOS Pull-Up Resistor LVTTL/ Input Leakage Current with LVCMOS Pull-Down Resistor
-0.5
0.7
V A
50
500
2.2VIIL ILEAK
-500
A A A A
-0.5V-10
10
ILEAK_PU ILEAK_PD
61.3
216
61.3
216
NOTE: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only.
SEREF OUTPUT CHARACTERISTICS
SYMBOL
VBB
PARAMETER
100 K Reference Bias Voltage
MIN
VDD_IO - 1.45
TYP
MAX
VDD_IO - 1.17
UNITS
V
CONDITIONS
NOTE: The SEREF output is designed to have maximum 30pF load capacitance, 750A sourcing and 1 mA sinking capability.
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XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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REV. P1.0.5
ORDERING INFORMATION
PART NUMBER
XRT91L82IB
PACKAGE
196 Shrink Thin Ball Grid Array (15.0 mm x 15.0 mm, STBGA)
OPERATING TEMPERATURE RANGE
-40C to +85C
196 SHRINK THIN BALL GRID ARRAY (15.0 MM X 15.0 MM, STBGA)
REV. 1.00
14 13
12 11 10
9
8
7
6
5
4
3
2
1
A1 Feature/Mark
A B C D E F G
D
D1
H J K L M N P
D1 D
(A1 corner feature is m fger option)
Seating Plane b A2 A1 A e
Note: The control dimension is in millimeter.
SYMBOL A A1 A2 D D1 b e
INCHES MIN MAX 0.053 0.067 0.010 0.022 0.033 0.052 0.585 0.596 0.512 BSC 0.018 0.022 0.039 BSC
MILLIMETERS MIN MAX 1.35 1.70 0.25 0.55 0.85 1.31 14.85 15.15 13.00 BSC 0.45 0.55 1.00 BSC
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REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REVISION HISTORY
REVISION #
P1.0.0 P1.0.1 P1.0.2
DATE
November 2004 Preliminary XRT91L82 datasheet. December 2004 Fixed pin-out discrepancies. January 2005
DESCRIPTION
1.Added CS de-assertion note on section 5.1. 2.Updated all registers and fixed register 0x02, 0x04, 0x05 microprocessor bit descriptions and modified several functional bit description for active low assertion and default settings. 3.Updated pin descriptions, corrected 'falling edge' typo error in section 3.6 to 'rising edge'. 4.Enhanced receive and transmit interface block diagrams and table formats in pin and microprocessor descriptions. 5.Corrected errors in Table 1 Reference Frequency Options. Removed 2.5V I/O support. 6.Remove 'RXSEL' reference on the RXIP/N pin description. 7.Minor edit in receive section 2.
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XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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REV. P1.0.5
REVISION HISTORY
REVISION #
P1.0.3
DATE
March 2005
DESCRIPTION
1.Moved microprocessor SDI pin from D10 to pin C10 and SCLK from D4 to pin D12. 2.Moved CP_OUT from pin F14 pin to pin F1 for Host Mode operation only. 3.Moved VCXO_IN from pin E14 to pin E4. 4.Removed IN_TERM in pin E4 to reflect enhanced internal bus termination support. 5.Added RXCAP1P and RXCAP1N/CP_OUT on pins E1 and F1 for external loop filter capacitors. 5.Added XRES1P and XRES1N LVDS biasing external resistors on pins E14 and F14. 6.Renamed RESETB, TXSCLKODIS, FIFO_RST/SCLK, REFREQSEL1, SEREF_EN, RLOOPS/PRBS_CLEAR, DLOOP, TX_SWING, TEST_MODE, PRBS_NOLOCK, RXCLKP/N, RXLCKREF, DISRD, DISRDCLK, LOSEXT pins to RESET, TXSCLKOOFF, FIFO_RST, REFREQSEL1/SCLK, SEREF_DIS, RLOOPS_PRBSCLR, DLOOP, TXSWING, PRBS_EN, PRBS_ERR, RXPCLKOP/N, RXLCKREF, DISRD, DISRDCLK, SDEXT respectively to reflect active low assertion and more precise functionality. 7.Renamed and updated bit description of VDD_3.3 to VDD_IO for 3.3V LVPECL /1.8V LVDS I/O references. 8.Updated STBGA pinout to include above mentioned changes. 9.Retouched 91L82 Block Diagram. 10.Corrected RXDO[15:0]P/N description error from 'updated on rising edge' to 'updated on falling edge' of RXPCLKOP/N. 11.Corrected PRBS_EN, FIFO_RST, TXSCLKOOFF description errors . 12.Removed unsupported note for transparent mode FIFO operation in section 3.3 and enhanced and corrected FIFO reset operation description. 13.Corrected Figure 14, "Loop Timing Mode Using an External Cleanup VCXO (Host Mode Only) 14.Added CMU and CDR performace tables. 15.Added CML input swing characteristics. 16.Added external loop filter and LVDS biasing resistor diagrams. 17.Added Data Latency in section 1.0. 18.Updated transmit and receive timing diagrams and timing table specifications. 19.Removed all references to limiting amplifier. 20.Significantly enhanced Signal Detection/LOS section description. 21.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accurately. Corrected and enhanced PISO and SIPO diagrams. 22.Added JTAG input pin pull-up and pull-down descriptions. 23.Moved FIFO figure from sect 3.6 to section 3.3. 24.Enlarged CML output swing figure. 25.Added directional arrows for RXIP/N and TXOP/N. 26.Added place holders for jitter performance charts. 27.Reformatted AC/DC electrical characteristics tables. 28.Rearrange Pin List format and formatted Table Header shading. 29.Added cross-reference for register bits and corrected mispellings and retouched bit descriptions. 30.Updated Microprocessor Register Bits and Descriptions to reflect changes. 31.Changed OC-48 to STS-48 name.
55
xr
REV. P1.0.5
PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
DATE
March 2005
REVISION HISTORY
REVISION #
P1.0.4
DESCRIPTION
1.Renamed RXLCKREF to CDRLCKREF and corrected pin and microprocessor bit description. 2.Reinstated INTERM pin on E4 to support Single-Ended LVPEL in Hardware Mode and added INTERM/VCXO_IN pin description. 3.Renamed AVDD1.8_RX, AVDD1.8_TX, VDD1.8 power and VSS ground pin connections to AVDD_RX, AVDD_TX, VDD_CMOS and GND respectively. 4.Split VDD_IO to VDD_IO and VDD_O and added pin description definition requiring 1.8V potential for VDD_O in LVDS operation. 5.Added ALTFREQSEL to support lower 77.76/83.31 MHz reference clocks, INTERM, and SEREFDIS in Host Mode. 6.Corrected LOOPTM_NOJA pin and microprocessor descripton. 7.Redesigned microprocessor registers. 8.Enhanced Section 7.0 Electrical Charateristics. 9.Enhanced Figure 1, "Block Diagram of XRT91L82. 10.Updated Figure 2, "196 BGA Pinout of THE XRT91L82 (Top View). 11.Corrected typos in pin description section and Figure 5, "External Loop Filter. 12.Enhanced Section 3.6 "Clock Multiplier Unit (CMU) and Re-Timer. 13.Updated Figure 14, "Loop Timing Mode Using an External Cleanup VCXO (Host Mode Only). 1.Changed VDD_O to VDD_IO and removed 1.8V potential requirement for LVDS operation. 2.Added internal termination and biasing notes in pin descriptions. 3.Moved microprocessor INT pin from C5 to pin D10 and SDO from C6 to pin E9. 4.Corrected REFREQSEL1/SCLK pin from D5 to D12. 5.In Host Mode, Added PRBS_LOCK on pin D4. Added PRBS Lock Interrupt Enable, Status, and Detection register bits. Added PRBS inversion capability. 6.Moved PRBS Enable register bit from D3 to D4 in register 0x05h. 7.Changed ALTFREQSEL and TXSWING register bit default values to "1." 8.Corrected Transmit Parallel Interface LVDS Operation section and moved to receive section 2.7. 9.Updated Figure 14 Loop Timing Mode Using an External Cleanup VCXO. 10.Revised and Updated Electrical Characteristics section 7.0
P1.0.5
April 2005
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet April 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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